A field-programmable gate array is a semiconductor device, which includes programmable logic components called “logic blocks” and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or simple mathematical functions. In most FPGA's, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memories. A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer. After the FPGA is manufactured, the system designer may use programming to implement many different logical functions, thereby making the device “field-programmable”.
A PLA is similar to a FPGA, except that the PLA is modified, or “programmed”, at the fabrication stage of the integrated circuits by changes in one or two masks. As described in U.S. Pat. No. 5,959,465, a PLA having flash EPROM memory elements is generally composed of two logic planes, an input plane and an output plane. Each plane receives inputs which are applied to gate terminals of transistors within the logic plane, and provides outputs to output nodes. The inputs to the input plane are the inputs to the PLA. The outputs of the input plane are intermediate nodes. The inputs to the output plane are connected to the intermediate nodes. The outputs of the output plane are the outputs of the PLA. The input plane may provide an AND function, and the output plane may provide an OR function. Alternatively, both planes may provide a NOR function. These functions are defined by the type and connectivity of the transistors used and the signals applied to their gates. The NOR-NOR configuration has particular advantages in that it is the simplest to implement in CMOS logic. NOR stages have a number of transistors equal to the number of inputs connected in parallel. Addition of further parallel transistors for accommodating further inputs does not affect the operating speed of the stage.
U.S. Pat. No. 6,876,228 describes a FPGA with magnetic storage elements or memory cells known as Magnetoresistive Random Access Memory (MRAM). Connection information is written to the magnetic storage elements. The connection information is serially input and stored in shift registers, which correspond to the magnetic storage elements. When the power is switched on, the connection information stored in the magnetic storage elements is latched by latch elements, and is output to switching circuits to interconnect the logic blocks of the FPGA.
Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that has response (read/write) times comparable to volatile memory. In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. As illustrated in FIGS. 1A and 1B, a magnetic tunnel junction (MTJ) storage element 105 can be formed from two magnetic layers 10 and 30, each of which can hold a magnetic field, separated by an insulating (tunnel barrier) layer 20. One of the two layers (e.g., fixed layer 10), is set to a particular polarity. The other layer's (e.g., free layer 30) polarity 32 is free to change to match that of an external field that can be applied. A change in the polarity 32 of the free layer 30 will change the resistance of the MTJ storage element 105. For example, when the polarities are aligned, FIG. 1A, a low resistance state exists. When the polarities are not aligned, FIG. 1B, then a high resistance state exists. The illustration of MTJ 105 has been simplified and those skilled in the art will appreciate that each layer illustrated may comprise one or more layers of materials, as is known in the art.